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Research interests

Design of asynchronous circuits, and in particular bundled-data protocols Simatic et al., 2016 and verification of such circuits Simatic et al., 2017.

High-level synthesis for event-based systems Simatic et al., 2016 and synchronous-to-asynchronous design conversion Bertrand et al., 2017Decoudu et al., 2020

Applications of event-driven circuits to signal processing, such as windowing techniques Qaisar et al., 2017, and finite-impulse response filters Simatic et al., 2015Skaf et al., 2017Decoudu et al., 2019.

PhD Thesis 2017

Title Design flow for ultra-low power: Non-uniform sampling and asynchronous circuits
Advisor Laurent Fesquet
Co-advisor Rodrigo Possamai Bastos

Abstract Integrated systems are mainly heterogeneous systems with strong power consumption constraints. They embed actuators, sensors and signal processing units. To limit the energy consumption, they can exploit event-based techniques, namely non-uniform sampling and asynchronous circuits. Indeed, they allow cutting drastically the amount of sampled data for many types of signals and reducing the system activity. To help designers in quickly developing platforms that exploit those event-based techniques, we elaborated a design framework called ALPS. It proposes an environment to determine and simulate at algorithmic level the sampling scheme and the associated processing in order to select the most efficient ones depending on the targetted application. ALPS generates directly the analog-to-digital converter based on the chosen sampling parameters. The elaboration of the processing unit uses a synchronous high-level synthesis tool and a desynchronization method that exploits specific asynchronous protocols to optimize the circuit area and power consumption. Finally, gate-level simulations allow analyzing and validating the energy consumption before continuing with a standard placement and routing flow. The conducted evaluations show a reduction factor of 3 to 8 of the consumption of the automatically generated circtuis. The flow ALPS allow non-specialists to concentrate on the optimization of the sampling and the processing in function of their application and to reduce the circuit power consumptions by one to several orders of magnitude.

References
  1. Simatic, J., Bastos, R. P., & Fesquet, L. (2016, June). High-level synthesis for event-based systems. 2016 Second International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP). 10.1109/ebccsp.2016.7605252
  2. Simatic, J., Cherkaoui, A., Bertrand, F., Bastos, R. P., & Fesquet, L. (2017, May). A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines. 2017 23rd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC). 10.1109/async.2017.16
  3. Bertrand, F., Cherkaoui, A., Simatic, J., Maure, A., & Fesquet, L. (2017, December). CAR: On the highway towards de-synchronization. 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS). 10.1109/icecs.2017.8292047
  4. Decoudu, Y., Simatic, J., Morin-Allory, K., & Fesquet, L. (2020). From High-Level Synthesis to Bundled-Data Circuits. In Embedded Computer Systems: Architectures, Modeling, and Simulation (pp. 200–212). Springer International Publishing. 10.1007/978-3-030-60939-9_14
  5. Qaisar, S. M., Simatic, J., & Fesquet, L. (2017, May). High-level synthesis of an event-driven windowing process. 2017 3rd International Conference on Event-Based Control, Communication and Signal Processing (EBCCSP). 10.1109/ebccsp.2017.8022807