Experience¶
Deeptech Startup Chief Technical Officer¶
🏢 HawAI.tech 🗓️ Feb 2019 - Ongoing 📍 Grenoble, FR
Manage 10‑person technical team (Scrum master then Product Owner).
Design of a modular architecture for low‑power probabilistic circuits.
Implementation in software, FPGA (AWS F1) and ACAP (Xilinx Versal) using RTL and HLS. Develop test fixtures (Python) and host code (Python/C++).
Install and maintain the company’s web services on cloud servers.
Electronics R&D engineer & Startup incubation¶
🏢 Probayes 🗓️ Jan 2018 - Feb 2019 📍 Grenoble, FR
Design highly efficient Bayesian sensor fusion and Bayesian filters using stochastic computing. Benchmark on Intel Cyclone V.
Lead legal, financial and business structuration for the spin‑off
Asynchronous circuits PhD candidate¶
🏛️ TIMA Laboratory 🗓️ Nov 2014 - Nov 2017 📍 Grenoble, FR
Parse synchrounous FSM (from AUGH HLS) and generate asynchronous bundle data controllers using new synchronization protocol.
Design and test circuits for non‑uniform sampling and filters.
Asynchronous circuits verification intern¶
🏢 Tiempo Secure 🗓️ April 2014 - Oct 2014 📍 Montbonnot Saint-Martin, FR
Design of a verification tool for standard cells Verilog modules
Evaluation of a commercial fault simulator on QDI circuits
Asynchronous circuit design intern¶
🏛️ Asynchronous Research Center 🗓️ April 2013 - Aug 2013 📍 Portland, Oregon, USA
Design of asynchronous IP for merge sort
Contribution to the development of a CAD tool (ARCWelder)
Education¶
University Grenoble Alpes¶
🏛️ TIMA Laboratory 🗓️ 2014 - 2017 📍 Grenoble, FR
🎓 PhD in circuit design/HLS
Design flow for ultra-low power: non-uniform sampling and asynchronous circuits
ENSTA ParisTech¶
🗓️ 2013 - 2014 📍 Palaiseau, France
🎓 Engineering - Robotics and Embedded Systems.
Multiprocessors on chip, embedded software, robotics, mecatronics.
University Pierre & Marie Curie¶
🗓️ 2013 - 2014 📍 Paris, France
🎓 Master of Science - Electronic systems and Computer systems
Mixed and analog circuit design, noise, design for test, MEMS
École polytechnique¶
🗓️ 2010 - 2013 📍 Palaiseau, France
🎓 Engineering - Electrical Engineering major
Digital circuit design, processor architecture, semi-conductors, optoelectronics, network (Internet), statistics
Skills¶
💻 Development¶
Python • Pytest • Pandas • Conda
C/C++ • Rust • Make • Shell • Tcl
Git • Subversion • VS Code • Emacs
Docker • Vagrant • Kubernetes
🤖 Digital electronic¶
Vivado • Vitis HLS • Vitis • Quartus
SystemVerilog • Verilog • VHDL • SystemC • VHDL‑AMS • Spice
DesignCompiler • PrimeTime • ModelSim • Innovus
I2C • SPI • AMBA • CAN
⚙️ Software¶
Ubuntu • ArchLinux • CentOS • Win
OVH cloud • AWS • SSH • Nginx
Jira • Confluence • LATEX• MS Office
💬 Languages¶
French: Native language
English: Fluent
German: Conversational
Portuguese: Conversational